1. Field of the Invention
Embodiments of the present invention relate generally to a semiconductor package and a method for manufacturing the same, and more particularly, to a bonding structure of a semiconductor package including a stack-type semiconductor package.
2. Description of the Related Art
As demand for miniaturization and high performance of electronic products increases in line with the increased demand for mobile products, the demand for a semiconductor memory with small size and large capacity has increased. One method for increasing storage capacity of a semiconductor memory includes mounting and assembling a plurality of semiconductor chips in one semiconductor package. In this method, only a packaging process may be changed to increase the storage capacity of the semiconductor memory. Furthermore, increasing storage capacity has a lot of advantages in terms of capital requirement, research and development, and development time. Therefore, semiconductor memory manufacturers have made a variety of attempts to increase the storage capacity of a semiconductor memory device through a multi-chip package having a plurality of semiconductor chips mounted in one semiconductor package.
Methods of mounting a plurality of semiconductor chips in one semiconductor package may include mounting a plurality of semiconductor chips in a horizontal direction and mounting a plurality of semiconductor chips in a vertical direction. Because of the characteristics of electronic products, to pursue miniaturization most semiconductor memory manufacturers prefer a stack-type multi-chip package in which a plurality of chips are vertically stacked and packaged. As an example of the stack-type multi-chip package, a package structure using through silicon vias (TSVs) has been proposed. The package employing TSVs allows for a plurality of semiconductor chips that are physically and electrically coupled in a vertical direction through TSVs which are formed in the respective semiconductor chips at a wafer level.
In a conventional stack-type package using TSVs, semiconductor chips having TSVs and a chip pad are electrically coupled through a bonding metal such as solder. However, when the semiconductor chips are stacked using TSVs, the TSVs are coupled through one signal and one link. Therefore, even though only one signal is cut, an open failure may occur. Accordingly, even though only one signal among several thousands of signals is cut, it may lead to failure of the entire product.